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[Engineering] 스탑워치 VHDL 설계

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작성일18-06-08 07:20

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Download : [공학] 스탑워치 VHDL 설계.hwp




[공학] 스탑워치 VHDL 설계 , [공학] 스탑워치 VHDL 설계공학기술레포트 , [공학] 스탑워치 VHDL 설계
[공학],스탑워치,VHDL,설계,공학기술,레포트
레포트/공학기술

설명






Download : [공학] 스탑워치 VHDL 설계.hwp( 82 )




순서

스탑워치 VHDL 설계

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity stop is

PORT(
CLK : in std_logic;
SW_A : in std_logic;
SW_B : in std_logic;
SW_C : in std_logic;
SW_D : in std_logic;
SEG_DATA : out std_logic_vector(7 downto -xxxx-xxxx);
SEG_COM : buffer std_logic_vector(7 downto -xxxx-xxxx)
);
end stop;

architecture arc of stop is

signal mode : std_logic_vector(2 downto -xxxx-xxxx);
signal SW_A_Q1, SW_A_Q2 : std_logic;
signal SW_B_Q1, SW_B_Q2 : std_logic;
signal SW_C_Q1, SW_C_Q2 : std_logic;
signal SW_D_Q1, SW_D_Q2 : std_logic;
signal msec : integer range -xxxx-xxxx to 9999;
signal seg5,seg6 : std_logic_vector(7 downto -xxxx-xxxx);
signal seg7,seg8 : std_logic_vector(7 downto -xxxx-xxxx);
signal temp : integer range -xxxx-xxxx to 9999;
signal temp1 : integer range -xxxx-xxxx to 9999;
signal cnt : integer range -xxxx-xxxx to 999;
function seven (display: integer range -xxxx-xxxx…(省略) to 1-xxxx-xxxx)
return std_logic_vector is
variable seg_data: std_logic_vector (7 downto -xxxx-xxxx);
begin
case display is
when -xxxx-xxxx 〓` seg_data :〓 `-xxxx-xxxx-xxxx-xxxx111111`;
when 1 〓` seg_data :〓 `-xxxx-xxxx-xxxx-xxxx-xxxx-xxxx-xxxx-xxxx-xxxx-xxxx11-xxxx-xxxx`;
when 2 〓` seg_data :〓 `xxx11-xxxx-xxxx11`;
when 3 〓` seg_data :〓 `xxx-xxxx-xxxx1111`;
when 4 〓` seg_data :〓 `-xxxx-xxxx11-xxxx-xxxx-xxxx-xxxx11-xxxx-xxxx`;
when 5 〓` seg_data :〓 `-xxxx-xxxx11-xxxx-xxxx11-xxxx-xxxx1`;
when 6 〓` seg_data :〓 `-xxxx-xxxx11111-xxxx-xxxx1`;
when 7 〓` seg_data :〓 `-xxxx-xxxxxxx-xxxx-xxxx111`;
when 8 〓` seg_data :〓 `-xxxx-xxxx1111111`;
when 9 〓` seg_data :〓 `-xxxx-xxxx11-xxxx-xxxx-xxxx-xxxx111`;
when others 〓` seg_data :〓 `-xxxx-xxxx-xxxx-xxxx-xxxx-xxxx-xxxx-xxxx-xxxx-xxxx-xxxx-xxxx-xxxx-xxxx-xxxx-xxxx`;
end case;
return seg_data;
end seven;

begin
SEG_COM(3 downto -xxxx-xxxx) `〓 `1111`;
process(CL
[Engineering] 스탑워치 VHDL 설계



[Engineering] 스탑워치 VHDL 설계

[공학]%20스탑워치%20VHDL%20설계_hwp_01_.gif [공학]%20스탑워치%20VHDL%20설계_hwp_02_.gif [공학]%20스탑워치%20VHDL%20설계_hwp_03_.gif [공학]%20스탑워치%20VHDL%20설계_hwp_04_.gif [공학]%20스탑워치%20VHDL%20설계_hwp_05_.gif [공학]%20스탑워치%20VHDL%20설계_hwp_06_.gif




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